There are many applications, including cameras, optical data transmitters, and optical data receivers, where electronic circuitry and optical devices are combined on a single integrated circuit.
It is also widely known that a significant limitation of modern processors and system-on-a-chip design is data transfer between functional units on a very large-scale integrated (VLSI) circuit; where resistance and capacitance of interconnect may significantly limit data rates.—An electro-optical interconnect may help solve this limitation on data rates. Further, many VLSI-based system designs suffer limitations on data rate due to the resistance of bondpad drivers and capacitance of chip-to-chip interconnect; electro-optical interconnects may prove a solution to this problem also. Furthermore, the energy per bit of electronic interconnects may place a power (thermal) budget limitation on the operation of an electronic microchip. Electro-optical interconnects may enable lower energy per bit interconnects. Finally, electrical interconnects may incur electrical cross-talk between adjacent wire lines that limits the spatial bandwidth density of interconnection to/from a chip. Optical interconnects may employ dense wavelength division multiplexing (DWDM) to achieve orders of magnitude higher bandwidth density without incurring significant cross-talk penalties. If on-chip optical interconnect is to become commonplace within large VLSI circuits, or inter-chip optical interconnect common within systems embodying multiple VLSI circuits, it is desirable to have efficient ways of coupling light into or out of the circuits, and to be able to route light from one part of a circuit to another.
Integrated photonics, including silicon photonics, has potential to enable electronic-photonic circuits with advanced optical signal processing functions and capabilities. One important area of application is energy-efficient photonic links for processor to memory chip communication, as well as chip-to-chip and on-chip interconnects. Other applications include active optical cables for rack-to-rack interconnects, transmitters and receivers for 100 Gbps Ethernet and beyond, as well as applications such as sensing, imaging (e.g. optical coherence tomography, etc.) and image/video projection applications, beam steering, and visible light biophotonic chips for high throughput biotechnology applications.
Integrated and silicon photonics typically employs customized fabrication processes. For silicon photonics, this typically means use of silicon-on-insulator (SOI) wafers with a large oxide thickness of 2-3 microns, and materials and/or lithography and process steps that are tailored to photonics, and not compatible with high density microelectronics.
Microelectronics, on the other hand, relies on carefully optimized complementary metal oxide semiconductor (CMOS) processes, such as those used for microprocessors and dynamic random access memory (DRAM) chips. A number of key potential applications for photonics are in state of the art CMOS logic chips including processors, and in DRAM memory chips.
Efficient optical fiber to on-chip waveguide coupling, and photonic vias for chip to chip, die to die, or layer to layer communication within a chip/die, would be desirable for commercially valuable photonic chip technology.
Furthermore, three-dimensional (3D) die stacking is a forthcoming integration technology that will result in chips comprising multiple die bonded together. An example is the Hybrid Memory Cube (HMC) (Trademark of Hybrid Memory Cube Consortium, Beaverton, Oreg.) technology for stacked memory chips. Electrical power and communication between dies in the stack may be done off-chip via wire bonding, or using through silicon vias (TSVs). For photonics to be fully enabled in such systems, efficient optical interconnection between device layers of several stacked die chips is desirable.